This invention relates to random access memories, and, more particularly, to the efficient utilization of a pseudo-static random access memory that must be periodically refreshed to avoid the loss of information stored in the memory.
Computers and other devices having a memory typically utilize Random Access Memory (RAM) to achieve fast access to stored information. From the standpoint of permanency of stored information, there are three principal types of RAM. Static Random Access Memory (SRAM) retains information in memory for an indefinite period of time without refreshing (recharging) of the state of the individual memory cells. Dynamic Random Access Memory (DRAM) retains information in memory only as long as the memory cells are continually refreshed. SRAM requires relatively complex individual memory cells, which are expensive and occupy large areas on chips or cards. DRAM is less expensive and space consuming, but requires potentially complex refresh circuitry that may be expensive and may slow the access of the host processor to the memory cell. SRAM has a low current consumption because it need not be refreshed, while DRAM has a relatively high current consumption because of the need for continual refreshing.
A compromise between these characteristics is achieved in a Pseudo-Static Random Access Memory (PSRAM). The PSRAM has a simpler memory cell than the SRAM, and is therefore less-expensive and smaller than the SRAM. The PSRAM requires periodic rather than continual refreshing, as is the case for DRAM. PSRAM is provided with internal refresh circuitry, and therefore requires less complex external refresh circuitry and permits better memory access for the host processor than DRAM. PSRAM provides the cost effectiveness of DRAM with the implementation ease of SRAM. PSRAM has a current consumption intermediate that of SRAM and DRAM, and is acceptable for use in both desk top and portable devices requiring memory. PSRAM memory is available in standard memory sizes from a number of manufacturers, including, for example, Hitachi, Toshiba, Samsung, and NEC.
In the case of a typical 4 megabit PSRAM, 2048 refresh cycles must be performed every 32 milliseconds. If the refresh cycles are not completed in that period, information can be lost from memory. During the refresh cycles, each of which typically lasts at least 150 nanoseconds, the memory is not available for accessing by the host computer or other device. Various internally generated refresh modes are available in the PSRAM memory chips themselves, but these refresh modes typically do not provide optimum access performance of the system that includes the host processor and the PSRAM. Since the designers of general purpose PSRAM chips cannot know the individual applications, the internally generated refresh modes are designed to avoid memory loss, not avoid memory loss while optimizing processor/PSRAM performance.
Thus, if allowed to operate on Its own, the PSRAM may perform far too many refresh cycles with some of the refresh cycles being performed when the processor seeks access to the memory. In each case the processor eventually gains access to the memory through an interruption of the refresh cycles. However, the processor is denied access to memory when the refresh cycles are being performed, slowing down the overall performance of the system. The delays in access to memory occasioned by the need to refresh the PSRAM, though individually small, can accumulate to have a significant effect on the speed of the processor system. Excessive numbers of refresh cycles also can consume excessive power, an important consideration if the PSRAM is used in a portable, battery-powered device.
There is a need for an approach to optimizing the performance of systems that utilize a host processor and PSRAM. The approach must ensure that the PSRAM is refreshed to avoid loss of stored information, while taking into consideration the memory access requirements of the host processor. The present invention fulfills this need, and further provides related advantages.